Since it launched in early March, AMD’s Ryzen 7 and Ryzen 5 families have blown holes in Intel’s midrange and high-end desktop product segments. It was only a matter of time until Chipzilla retaliated, and a leaked slide from a German presentation suggests that Intel is stepping up its own Skylake-X HEDT (High End DeskTop) platforms.
According to the leaked information, Intel will offer a top-end 12-core Core i9-7920X, with 24 threads and 16.5MB of L3 cache, with 44 PCIe 3.0 lanes. Base clock and turbo frequencies are all TBD, but the chip supposedly has 16.5MB of L3 cache. The other chips are listed as follows:
Core i9-7900X: 10 cores, 20 threads, 3.3GHz base, 4.3GHz Turbo, 4.5GHz Turbo Boost 3.0, 13.75MB of L3, 44 lanes of PCIe 3.0.
Core i9-7820X: 8 cores, 16 threads, 3.6GHz base, 4.3GHz Turbo, 4.5GHz Turbo Boost 3.0, 11MB L3, 28 lanes of PCIe 3.0
Core i9-7800X: 6 cores, 12 threads, 3.5GHz base, 4GHz Turbo, no Turbo Boost 3.0, 8.25MB L3, 28 lanes of PCIe 3.0.
Core i7-7740K: 4 cores, 8 threads, 4.3GHz base, 4.5GHz Turbo, no Turbo Boost 3.0, 8MB L3, 16 lanes of PCIe 3.0.
Core i7-7640K: 4 cores, 4 threads, 4GHz base, 4.2GHz Turbo, no Turbo Boost 3.0, 6MB of L3 cache, 16 lanes of PCIe 3.0.
The two Core i7 chips would be Kaby Lake-derived while the rest of the Core i9 family is based on Skylake-X.
No clean match with existing Intel products
I’m not at all certain these leaks reflect the chips Intel will announce at Computex. First, there’s the amount of L3 cache. These new cores have far less L3 cache than any current Intel HEDT chip — Intel’s 10-core 6950X, for example, has 25MB of L3. For the last six years, all the way back to the 3960X, Intel has offered 2-2.5MB of L3 cache per CPU core in the HEDT family. These new chips slash that ratio to 1.375MB per core.
Sweepr, the Anandtech poster who leaked this information, claims that Intel has made up for the sharp L3 deficit by quadrupling the size of its L2 cache. While we’ve talked before about how Intel might respond to AMD’s Ryzen, there’s no way Intel could have possibly made this change in response. Increasing cache sizes without negatively impacting cache latency is a significant undertaking; Intel would have had to do a fundamental respin on Skylake to make this change. If these cache counts are accurate, they reflect plans Intel made a year or more ago, not any recent response to a renewed competitive environment. And how effective (and how large) various caches need to be for optimal performance is partially a function of the cache architecture. Increasing the L2 cache by 768KB doesn’t automatically compensate for shrinking the L3 cache.
If this leaked roadmap is true–and that’s a big if–it implies Intel won’t be fixing one of the artificial segmentation barriers that’s most annoyed enthusiasts: the lockout on PCI Express lanes. If you want to run two graphics cards at full x16, you have to buy a 10-core chip to do it. Unless Intel plans to substantially slash prices, that would actually be a worse deal than at present. Currently, the Core i7-6850K supports 40 PCI-Express lanes with an MSRP of $ 617 – $ 628. Intel’s 10-core processor, the 6950X, is a $ 1,800 core. Unless Intel plans a serious price cut at this core count, enthusiasts will have to pay top dollar for a 32-lane solution. Ryzen 7 doesn’t currently offer a 32-lane solution either, though there’s speculation that the company’s rumored HEDT competitive solution will, when and if it’s released.
Finally, it’s not clear why Intel would even bother releasing Core i7 CPUs with these specs. There’s the tiniest hint of an upgrade in the i7-7740K, with its 4.3GHz base clock as opposed to the 4.2GHz base clock of the 7700K, but the Core i7-7640K isn’t an i7 at all. It’s nothing but an i5 with higher base clocks, and any four-core / eight-thread i7 from the past few years will outperform it in any multi-threaded application of note. Releasing an entry-level HEDT “Core i7” that would assuredly be outperformed by the Core i7-4790K, 6700K, or 7700K isn’t the best way to encourage enthusiast adoption and I’m taking these rumors with a fair bit of salt.
Now read: How L1 and L2 CPU caches work, and why they’re an essential part of modern chips
Let’s block ads! (Why?)